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general description the max15034 two-phase, configurable single- or dual- output buck controller has an input voltage range of 4.75v to 5.5v or 5v to 28v. a mode select input allows for a dual-output supply or connecting two phases together for a single-output, high-current supply. each output channel of the max15034 drives n-channel mosfets and is capable of providing more than 25a of load current. the max15034 uses average current- mode control with a switching frequency up to 1mhz per phase where each phase is 180 out of phase with respect to the other. out-of-phase operation results in significantly reduced input capacitor ripple current and output voltage ripple in dual-phase, single-output volt- age applications. each controller has its own high-per- formance current and voltage-error amplifier that can be compensated for optimum output filter l-c values and transient response. the max15034 offers two enable inputs with accurate turn-on thresholds to allow for output voltage sequencing of the two outputs. the devices switching frequency can be programmed from 100khz to 1mhz with an external resistor. the max15034 can be synchronized to an external clock. each output voltage is adjustable from 0.61v to 5.5v. additional features include thermal shut- down and hiccup-mode, short-circuit protection. use the max15034 with adaptive voltage positioning for applica- tions that require a fast transient response or accurate output voltage regulation. the max15034 is available in a thermally enhanced 28- pin tssop package capable of dissipating 2.1w. the device is rated for operation over the -40c to +125c automotive temperature range. applications high-end computers/workstations/servers graphics cards networking systems point-of-load high-current/high-density telecom dc-dc regulators raid systems features 4.75v to 5.5v or 5v to 28v input dual-output synchronous buck controller configurable for two separate outputs (25a) or one single output (50a) average current-mode control with accurate adjustable current limit 180 interleaved operation reduces size of input filter capacitors limits reverse current sinking when operated in parallel mode each output is adjustable from 0.61v to 5.5v independently programmable adaptive voltage positioning monotonic startup into prebiased outputs independent shutdown for each output 100khz to 1mhz per phase programmable switching frequency oscillator frequency synchronization from 200khz to 2mhz digital soft-start on outputs hiccup-mode overcurrent protection overtemperature shutdown thermally enhanced 28-pin tssop package capable of dissipating 2.1w max15034 configurable, single-/dual-output, synchronous buck controller for high-current applications ________________________________________________________________ maxim integrated products 1 ordering information 19-4218; rev 1; 10/11 for pricing, delivery, and ordering information, please contact maxim direct at 1-888-629-4642, or visit maxim? website at www.maxim-ic.com. part temp range pin-package max15034aaui+ -40c to +125c 28 tssop max15034baui+ -40c to +125c 28 tssop-ep* max15034baui/v+ -40c to +125c 28 tssop-ep* + denotes a lead(pb)-free/rohs-compliant package. * ep = exposed pad. /v denotes an automotive qualified part. evaluation kit available
max15034 configurable, single-/dual-output, synchronous buck controller for high-current applications 2 _______________________________________________________________________________________ absolute maximum ratings stresses beyond those listed under ?bsolute maximum ratings?may cause permanent damage to the device. these are stress rating s only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specificatio ns is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. in, lx_ to agnd.....................................................-0.3v to +30v bst_ to agnd........................................................-0.3v to +35v dh_ to lx_ ....................................-0.3v to (v bst_ - v lx_ ) + 0.3v dl_ to pgnd ..............................................-0.3v to (v dd + 0.3v) bst_ to lx_ ..............................................................-0.3v to +6v v dd to pgnd............................................................-0.3v to +6v agnd to pgnd .....................................................-0.3v to +0.3v avglimit, reg, rt/clkin, csp_, csn_ to agnd ......................................................-0.3v to +6v all other pins to agnd ............................-0.3v to (v reg + 0.3v) reg continuous output current (limited by power dissipation, no thermal or short-circuit protection).........................................................................67ma continuous power dissipation (t a = +70?) (note 1) 28-pin tssop (derate 14mw/? above +70?) ..........1117mw 28-pin tssop-ep (derate 27mw/? above +70?) ........ 2162mw operating temperature range .........................-40? to +125? maximum junction temperature .....................................+150? storage temperature range .............................-60? to +150? lead temperature (soldering, 10s) .................................+300? soldering temperature (reflow) .......................................+260? electrical characteristics (v in = v reg = v dd = v en_ = +5v, t a = t j = t min to t max , unless otherwise noted, circuit of figure 6. typical values are at t a = +25?.) (note 2) parameter symbol conditions min typ max units system specifications 528 input voltage range v in in and reg shorted together for +5v operation 4.75 5.50 v quiescent supply current i in f osc = 500khz, dh_ or dl_ = open 7 17 ma startup/internal regulator output (reg) reg undervoltage lockout uvlo v reg rising 4.0 4.15 4.5 v hysteresis v hyst 200 mv reg output accuracy v in = 5.8v to 28v, i source = 0 to 65ma 4.75 5.10 5.30 v reg dropout v in < 5.8v, i source = 60ma 0.5 v internal reference internal reference voltage v ean_ ean_ connected to eaout_ (note 3) t a = -40? to +125? 0.605 0.6125 0.620 v digital ramp period for soft-start 1024 clock cycles soft-start voltage steps 64 steps mosfet drivers p-channel output driver impedance r on_p 1.35 3 ? note 1: package thermal resistances were obtained using the method described in jedec specification jesd51-7, using a four- layer board. for detailed information on package thermal considerations, refer to www.maxim-ic.com/thermal-tutorial . package thermal characteristics (note 1) tssop junction-to-ambient thermal resistance ( ja )..................71.6?/w junction-to-case thermal resistance ( jc )......................13?/w tssop-ep junction-to-ambient thermal resistance ( ja )..................37?/w junction-to-case thermal resistance ( jc )......................2?/w
max15034 configurable, single-/dual-output, synchronous buck controller for high-current applications _______________________________________________________________________________________ 3 electrical characteristics (continued) (v in = v reg = v dd = v en_ = +5v, t a = t j = t min to t max , unless otherwise noted, circuit of figure 6. typical values are at t a = +25c.) (note 2) parameter symbol conditions min typ max units n-channel output driver impedance r on_n 0.45 1.35 ? output driver source current i dh_ , i dl_ 2.5 a output driver sink current i dh_ , i dl_ 5a c dh_ or c dl_ = 5nf -7.5 +7.5 nonoverlap time (dead time) t no f sw = 1mhz nominal, r rt = 12.4k ? -10 +10 % rt/clkin output voltage v rt/clkin 1.225 v rt/clkin current sourcing capability i rt/clkin 0.5 ma rt/clkin logic-high threshold v rt/clkin_h 2.4 v rt/clkin logic-low threshold v rt/clkin_l 0.8 v rt/clkin high pulse width t rt/clkin 30 ns rt/clkin synchronization frequency range f rt/clkin 200 2000 khz current limit internal average current-limit threshold v cl_ v csp_ - v csn_ 20.4 22.5 24.75 mv reverse average current-limit threshold v rcl_ v csp_ - v csn_ -3.0 -1.53 -0.1 mv external average current-limit threshold adjustment v cl_adj resistor-divider connected from reg to avglimit to agnd v avglimit - 0.6/36 v avglimit ground threshold voltage v avglimit_gnd 550 mv leakage current at avglimit i avglimit v avglimit = 3v 100 na digital fault integration (df_) number of switching cycles to shutdown in current limit ns df_ 32,768 clock cycles number of switching cycles to recover from shutdown nr df_ 524,288 clock cycles current-sense amplifier csp_ to csn_ input resistance r cs_ 3.8 k ? v in = v reg = 4.75v to 5.5v or v in = 5v to 10v -0.3 +3.6 v common-mode range v cmr(cs) v in = 7v to 28v -0.3 +5.5 v input offset voltage v os(cs) 100 v amplifier gain a v(cs) 36 v/v
max15034 configurable, single-/dual-output, synchronous buck controller for high-current applications 4 _______________________________________________________________________________________ electrical characteristics (continued) (v in = v reg = v dd = v en_ = +5v, t a = t j = t min to t max , unless otherwise noted, circuit of figure 6. typical values are at t a = +25c.) (note 2) parameter symbol conditions min typ max units -3db bandwidth f -3db 4 mhz v csp_ = 5.5v, sinking 120 csp_ input bias current i csa(in) v csp_ = 0v, sourcing 30 a current-error amplifier (cea_) transconductance g m 550 s open-loop gain a vol(cea) no load 50 db voltage-error amplifier (eaout_) open-loop gain a vol(ea) 70 db unity-gain bandwidth f ugea 3 mhz ean_ input bias current i bias(ea) v ean_ = 2.0v 100 na error-amplifier output clamping high voltage v c lm p_h i (e a) with respect to v cm 1v error-amplifier output clamping low voltage v c lm p_lo ( ea ) with respect to v cm -0.234 v en_ inputs en_ input high voltage v enh en rising 1.2 1.222 1.245 en_ hysteresis 0.05 v en_ input leakage current i en -200 +200 na startup delay time to out_ t start_delay from en_ rising to v out_ rising 1 ms mode input mode logic-high threshold v mode_h 2.4 v mode logic-low threshold v mode_l 0.8 v mode input pulldown i pulldwn 5a prebiased output peak sink current-limit threshold during reference soft-start v csp_ - v csn_ -2.1 mv digital ramp period for stepping peak sink current limit after reference soft-start 448 clock cycles thermal shutdown thermal shutdown t shdn 160 thermal shutdown hysteresis t hyst 10 c note 2: the device is 100% production tested at t a = t j = +125c. limits at t a = -40c and t a = +25c are guaranteed by design. note 3: the internal reference voltage accuracy is measured at the negative input of the error amplifiers (ean_). output voltage accuracy must include external resistor-divider tolerances.
max15034 configurable, single-/dual-output, synchronous buck controller for high-current applications oscillator frequency vs. r t max15034 toc01 r t (k ? ) oscillator frequency (khz) 900 800 700 600 500 400 300 200 100 100 1000 10,000 10 0 1000 c dh_ = c dl_ = 0 supply current vs. temperature and frequency (v in = 5v) max15034 toc02a temperature ( c) supply current (ma) 110 95 -25 -10 5 35 50 65 20 80 2 4 6 8 10 12 14 16 0 -40 125 c dh_ = c dl_ = 0 f sw = 1mhz f sw = 250khz f sw = 500khz f sw = 125khz supply current vs. temperature and frequency (v in = 12v) max15034 toc02b temperature ( c) supply current (ma) 110 95 -25 -10 5 35 50 65 20 80 2 4 6 8 10 12 14 16 0 -40 125 c dh_ = c dl_ = 0 f sw = 1mhz f sw = 250khz f sw = 500khz f sw = 125khz supply current vs. temperature and frequency (v in = 24v) max15034 toc02c temperature ( c) supply current (ma) 110 95 -25 -10 5 35 50 65 20 80 2 4 6 8 10 12 14 16 0 -40 125 c dh_ = c dl_ = 0 f sw = 1mhz f sw = 250khz f sw = 500khz f sw = 125khz supply current vs. oscillator frequency max15034 toc03 frequency (khz) supply current (ma) 1800 1600 400 600 800 1200 1000 1400 7 8 9 10 11 12 13 14 6 200 2000 c dh_ = c dl_ = 0 v in = 24v v in = 5v v in = 12v supply current vs. driver load capacitance max15034 toc04 c load (nf) supply current (ma) 25 20 15 10 5 10 20 30 40 50 60 70 80 90 100 0 030 c load = c dh_ = c dl_ reg load regulation max15034 toc05 i reg (ma) v reg (v) 90 80 70 60 50 40 30 20 10 4.95 5.00 5.05 5.10 4.90 0100 v in = 12v v in = 24v v in = 5.5v reg line regulation max15034 toc06 v in (v) v reg (v) 23 21 19 17 15 13 11 9 7 4.98 5.00 5.02 5.04 5.06 5.08 5.10 4.96 5 i reg = 0 i reg = 60ma output load-transient response max15034 toc07 2ms/div 10a/div i out v out 100mv/div ac-coupled 20a typical operating characteristics (circuit of figure 6, t a = +25c, unless otherwise noted. v in = 12v, v out1 = 0.8v, v out2 = 1.3v, f sw = 500khz per phase.) _______________________________________________________________________________________ 5
max15034 configurable, single-/dual-output, synchronous buck controller for high-current applications 6 _______________________________________________________________________________________ driver rise time vs. load capacitance max15034 toc08 c load (nf) t rise (ns) 20 18 14 16 4 6 8 10 12 2 10 20 30 40 50 60 70 80 90 100 0 022 dl_ dh_ driver fall time vs. load capacitance max15034 toc09 c load (nf) t fall (ns) 20 18 14 16 4 6 8 10 12 2 5 10 15 20 25 30 35 40 0 022 dl_ dh_ high-side driver rise time (v in = 12v, c load = 10nf) max15034 toc10 dh_ 2v/div 20ns/div high-side driver fall time (v in = 12v, c load = 10nf) max15034 toc11 dh_ 2v/div 20ns/div low-side driver rise time (v in = 12v, c load = 10nf) max15034 toc12 dl_ 2v/div 20ns/div low-side driver fall time (v in = 12v, c load = 10nf) max15034 toc13 dl_ 2v/div 20ns/div typical operating characteristics (continued) (circuit of figure 6, t a = +25c, unless otherwise noted. v in = 12v, v out1 = 0.8v, v out2 = 1.3v, f sw = 500khz per phase.)
max15034 configurable, single-/dual-output, synchronous buck controller for high-current applications turn-on/turn-off waveform max15034 toc15 1ms/div v out1 1v/div en1 5v/div en2 5v/div v out2 1v/div _______________________________________________________________________________________ 7 out1/out2 out-of-phase waveforms (v out1 = 0.8v, v out2 = 1.3v) max15034 toc14 out1 100mv/div 10 s/div out2 100mv/div lx2 10v/div lx1 10v/div typical operating characteristics (continued) (circuit of figure 6, t a = +25c, unless otherwise noted. v in = 12v, v out1 = 0.8v, v out2 = 1.3v, f sw = 500khz per phase.) short-circuit current waveforms (v in = 5v) max15034 toc16 200ms/div i out2 10a/div i out1 10a/div average current limit vs. v avglimit max15034 toc17 v avglimit (v) average current limit (mv) 15 30 45 60 75 0 2.5 2.0 1.5 1.0 0.5 0 3.0 internal reference voltage vs. temperature max15034 toc18 temperature ( c) internal reference voltage (v) 110 95 80 65 50 35 20 5 -10 -25 0.610 0.615 0.620 0.605 -40 125 switching frequency vs. temperature max15034 toc19 temperature ( c) switching frequency (khz) 475 500 525 550 450 110 95 80 65 50 35 20 5 -10 -25 -40 125
max15034 configurable, single-/dual-output, synchronous buck controller for high-current applications 8 _______________________________________________________________________________________ typical operating characteristics (continued) (circuit of figure 6, t a = +25c, unless otherwise noted. v in = 12v, v out1 = 0.8v, v out2 = 1.3v, f sw = 500khz per phase.) soft-start waveform max15034 toc22 400 s/div en2 5v/div v out2 500mv/div v ean2 200mv/div prebiased output condition max15034 toc23 400 s/div en2 5v/div 0v v out2 500mv/div dh2 5v/div dl2 5v/div eaout2 1v/div internal average current limit vs. temperature max15034 toc20 temperature ( c) internal average current limit (mv) 21 22 23 24 25 20 110 95 80 65 50 35 20 5 -10 -25 -40 125 internal average reverse current limit vs. temperature max15034 toc21 internal average current limit (mv) -2.5 -2.0 -1.5 -1.0 -0.5 0 -3.0 temperature ( c) 110 95 80 65 50 35 20 5 -10 -25 -40 125 peak pullup and pulldown current or driver at dh_ and dl_ max15034 toc24 200ns/div c load = 10nf dh_ 500mv/div dl_ 500mv/div
max15034 configurable, single-/dual-output, synchronous buck controller for high-current applications _______________________________________________________________________________________ 9 pin description pin name function 1 csn2 current-sense differential amplifier negative input for output 2. connect csn2 to the negative terminal of the sense resistor. the differential voltage between csp2 and csn2 is internally amplified by the current- sense amplifier (a v(cs) = 36v/v). 2 csp2 current-sense differential amplifier positive input for output 2. connect csp2 to the positive terminal of the sense resistor. the differential voltage between csp2 and csn2 is internally amplified by the current-sense amplifier (a v(cs) = 36v/v). 3 eaout2 voltage error-amplifier output 2. connect to an external gain-setting feedback resistor. the error-amplifier gain determines the output voltage load regulation for adaptive voltage positioning. this output also serves as the compensation network connection from eaout2 to ean2. a resistive network results in a drooped output-voltage-regulation characteristic. an integrator configuration results in very tight output-voltage regulation (see the adaptive voltage positioning section). 4 ean2 voltage error-amplifier inverting input for output 2. connect a resistive divider from v out2 to ean2 to agnd to set the output voltage. a compensation network connects from eaout2 to ean2. a resistive network results in a drooped output-voltage-regulation characteristic. an integrator configuration results in very tight output-voltage regulation (see the adaptive voltage positioning section). 5 clp2 current-error amplifier output 2. compensate the current loop by connecting an r-c network from clp2 to agnd. 6 avglimit average current-limit programming. connect a resistor-divider between reg, avglimit, and agnd to set the average current-limit value (see the programming average the current limit section). 7 rt/clkin external clock input or internal frequency-setting connection. connect a resistor from rt/clkin to agnd to set the switching frequency. connect an external clock at rt/clkin for external frequency synchronization. 8 agnd analog ground 9 mode mode function input. mode selects between a single-output dual phase or a dual-output buck regulator. when mode is grounded, vea1 and vea2 connect to cea1 and cea2, respectively (see figure 1) and the device operates as a two-output, out-of-phase buck regulator. when mode is connected to reg (logic high), vea2 is disconnected and vea1 is routed to both cea1 and cea2. 10 clp1 current-error amplifier output 1. compensate the current loop by connecting an r-c network from clp1 to agnd. 11 ean1 voltage error-amplifier inverting input for output 1. connect a resistive divider from v out1 to ean1 to regulate the output voltage. a compensation network connects from eaout1 to ean1. a resistive network results in a drooped output-voltage-regulation characteristic. an integrator configuration results in very tight output-voltage regulation (see the adaptive voltage positioning section). 12 eaout1 voltage error-amplifier output 1. connect to an external gain-setting feedback resistor. the error-amplifier gain determines the output-voltage-load regulation for adaptive voltage positioning. this output also serves as the compensation network connection from eaout1 to ean1. a resistive network results in a drooped output-voltage-regulation characteristic. an integrator configuration results in very tight output-voltage regulation (see the adaptive voltage positioning section). 13 csp1 current-sense differential amplifier positive input for output 1. connect csp1 to the positive terminal of the sense resistor. the differential voltage between csp1 and csn1 is internally amplified by the current-sense amplifier (a v(cs) = 36v/v). 14 csn1 current-sense differential amplifier negative input for output 1. connect csn1 to the negative terminal of the sense resistor. the differential voltage between csp1 and csn1 is internally amplified by the current- sense amplifier (a v(cs) = 36v/v).
max15034 configurable, single-/dual-output, synchronous buck controller for high-current applications 10 ______________________________________________________________________________________ detailed description the max15034 switching power-supply controller can be configured two ways. with the mode input high, this device operates as single-output, dual-phase, step- down switching regulators where each output is 180 out of phase. with mode connected low, the max15034 operates as a dual-output, step-down switching regulator. the average current-mode control topology of the max15034 offers high-noise immunity while having benefits similar to those of peak current- mode control. average current-mode control has the intrinsic ability to accurately limit the average current sourced by the converter during a fault condition. when a fault condition occurs, the error-amplifier output volt- age (eaout1 or eaout2) that connects to the positive input of the transconductance amplifier (ca1 or ca2) is clamped, thus limiting the output current. the max15034 has internal logic to ensure each outputs monotonic startup under prebias load conditions. this facilitates glitch-free output voltage power-up in the pres- ence of another redundant/parallel voltage regulator. the max15034 contains all blocks necessary for two independently regulated average current-mode pwm regulators. this device has two voltage error amplifiers (vea1 and vea2), two current-error amplifiers (cea1 and cea2), two current-sensing amplifiers (ca1 and ca2), two pwm comparators (cpwm1 and cpwm2), and drivers for both low- and high-side power mosfets (see figure 1). each pwm section is also equipped with a pulse-by-pulse, current-limit protection and a fault integration block for hiccup protection. pin description (continued) pin name function 15 en1 output 1 enable. a logic-low shuts down channel 1s mosfet drivers. en1 can be used for output sequencing. 16 bst1 boost flying-capacitor connection. reservoir capacitor connection for the high-side mosfet driver supply. connect a 0.47f ceramic capacitor between bst1 and lx1. 17 dh1 high-side gate driver output 1. dh1 drives the gate of the high-side mosfet. 18 lx1 external inductor connection and source connection for the high-side mosfet for output 1. lx1 also serves as the return terminal for the high-side mosfet driver. 19 dl1 low-side gate driver output 1. gate driver output for the synchronous mosfet. 20 v dd supply voltage for low-side drivers. reg powers v dd . connect a parallel combination of 0.1f and 1f ceramic capacitors from v dd to pgnd and a 1 ? resistor from v dd to reg to filter out the high-peak currents of the driver from the internal circuitry. 21 reg internal 5v regulator output. reg is derived internally from in and is used to power the internal bias circuitry. bypass reg to agnd with a 4.7f ceramic capacitor. 22 in supply voltage connection. connect in to a 5v to 28v input supply. 23 pgnd power ground. source connection for the low-side mosfet. connect v dd s bypass capacitor returns to pgnd. 24 dl2 low-side gate driver output 2. gate driver for the synchronous mosfet. 25 lx2 external inductor connection and source connection for the high-side mosfet for output 2. also serves as the return terminal for the high-side mosfet driver. 26 dh2 high-side gate driver output 2. dh2 drives the gate of the high-side mosfet. 27 bst2 boost flying-capacitor connection. reservoir capacitor connection for the high-side mosfet driver supply. connect a 0.47f ceramic capacitor between bst2 and lx2. 28 en2 output 2 enable. a logic-low shuts down channel 2s mosfet drivers. en2 can be used for output sequencing. ep exposed pad. connect exposed pad to ground plane (max15034baui only).
max15034 two enable comparators (cen1 and cen2) are avail- able to control and sequence the two pwm sections through the enable (en1 or en2) inputs. an oscillator, with an externally programmable frequency generates two clock pulse trains and two ramps for both pwm sections. the two clocks and the two ramps are 180 out of phase with each other. a linear regulator (reg) generates the 5v to supply the device. this regulator has the output-current capability necessary to provide for the max15034s internal circuitry and the power for the external mosfets gate drivers. internal uvlo circuitry ensures that the max15034 starts up when v reg is at the correct volt- age levels to guarantee safe operation of the ic and of the power mosfets. finally, a thermal-shutdown feature protects the device during thermal faults and shuts down the max15034 when the die temperature exceeds +160c. 16 17 18 19 bst1 dh1 lx1 dl1 20 27 26 25 24 23 bst2 dh2 lx2 dl2 pgnd v dd 2 csp2 1 csn2 13 csp1 14 csn1 ca1 11 ean1 6 avglimit agnd 8 en1 15 en2 28 ca2 cpwm1 cpwm2 7 rt/clkin cea1 cea2 12 eaout1 9 mode 3 eaout2 5 clp2 10 clp1 22 in 21 reg 1.225v 1.225v thermal shutdown v dd mux 4 ean2 cen1 vea1 df1 and hiccup logic external frequency sync 0 control and driver logic 1 control and driver logic 2 df2 and hiccup logic oscillator and phase splitter 180 2v p-p ramp v reg = 5v for internal biasing uvlo v intref = 0.61v vea2 cen2 2v p-p ramp figure 1. block diagram configurable, single-/dual-output, synchronous buck controller for high-current applications ______________________________________________________________________________________ 11
max15034 configurable, single-/dual-output, synchronous buck controller for high-current applications 12 ______________________________________________________________________________________ dual-output/dual-phase select (mode) the max15034 can operate as a dual-output, indepen- dently regulated buck converter, or as a dual-phase, single-output buck converter. the mode input selects between the two operating modes. when mode is grounded (logic-low), vea1 and vea2 connect to cea1 and cea2, respectively (see figure 1), and the device operates as a two-output dc-dc converter. when mode is connected to reg (logic-high), vea2 is dis- connected and vea1 is routed to both cea1 and cea2 and the device works as a dual-phase, single-output buck regulator with each output 180 out of phase with respect to each other. supply voltage connections (v in /v reg ) the max15034 accepts a wide input voltage range at in of 5v to 28v. an internal linear regulator steps down v in to 5.1v (typ) and provides power to the max15034. the output of this regulator is available at reg. for v in = 4.75v to 5.5v, connect in and reg together external- ly. reg can supply up to 65ma for external loads. bypass reg to agnd with a 4.7f ceramic capacitor for high-frequency noise rejection and stable operation. reg supplies the current for the max15034s internal circuitry and for the mosfet gate drivers (when con- nected externally to v dd ), and can source up to 65ma. calculate the maximum bias current (i bias ) for the max15034: where i in is the quiescent supply current into in (4ma, typ), q gq1 , q gq2 , q gq3 , q gq4 are the total gate charges of mosfets q1 through q4 at v gs = 5v (see figure 6), and f sw is the switching frequency of each individual phase. low-side mosfet driver supply (v dd ) v dd is the power input for the low-side mosfet dri- vers. connect the regulator output reg externally to v dd through an r-c lowpass filter. use a 1 ? resistor and a parallel combination of 1f and 0.1f ceramic capacitors to filter out the high peak currents of the mosfet drivers from the sensitive internal circuitry. high-side mosfet drive supply (bst_) bst1 and bst2 supply the power for the high-side mosfet drivers for output 1 and output 2, respectively. connect bst1 and bst2 to v dd through rectifier diodes d1 and d2 (see figure 6). connect a 0.1f ceramic capacitor between bst_ and lx_. minimize the trace inductance from bst_ and v dd to the rectifier diodes, d1 and d2, and from bst_ and lx_ to the boost capacitors, c8 and c9 (see figure 6). this is accomplished by using short, wide trace lengths. undervoltage lockout (uvlo)/ power-on reset (por)/soft-start the max15034 includes an undervoltage lockout (uvlo) with hysteresis, and a power-on reset circuit for converter turn-on and monotonic rise of the output volt- age. the uvlo threshold monitors v reg and is inter- nally set between 4.0v and 4.5v with 200mv of hysteresis. hysteresis eliminates chattering during startup. most of the internal circuitry, including the oscillator, turns on when v reg reaches 4.5v. the max15034 draws up to 4ma (typ) of current before v reg reaches the uvlo threshold. the compensation network at the current-error ampli- fiers (clp1 and clp2) provides an inherent soft-start of the output voltage. it includes (r14 and c10) in parallel with c11 at clp1 and (r15 and c12) in parallel with c13 at clp2 (see figure 6). the voltage at the current- error amplifier output limits the maximum current avail- able to charge the output capacitors. the capacitor at clp_ in conjunction with the finite output-drive current of the current-error amplifier yields a finite rise time for the output current and thus, the output voltage. setting the switching frequency (f sw ) an internal oscillator generates the 180 o out-of-phase clock signals required for both pwm modulators. the oscillator also generates the 2v p-p voltage ramps nec- essary for the pwm comparators. the oscillator fre- quency can be set from 200khz to 2mhz by an external resistor (r t ) connected from rt/clkin to agnd (see figure 6). the equation below shows the relationship between r t and the switching frequency: where r rt is in ohms and the per-phase switching fre- quency is f sw = f osc /2. use rt/clkin as a clock input to synchronize the max15034 to an external frequency (f rt/clkin ). applying an external clock to rt/clkin allows each pwm section to work at a frequency equal to f rt/clkin /2. an internal comparator with a 1.6v thresh- old detects f rt/clkin . if f rt/clkin is present, internal logic switches from the internal oscillator clock, to the clock present at rt/clkin. f r hz osc rt = 25 10 10 . iifqqqq bias in sw gq gq gq gq =+ +++ () 1234
max15034 configurable, single-/dual-output, synchronous buck controller for high-current applications ______________________________________________________________________________________ 13 hiccup fault protection the max15034 includes overload fault protection circuitry that prevents damage to the power mosfets. the fault protection consists of two digital fault integration blocks that enable hiccuping under overcurrent conditions. this circuit works as follows: for every clock cycle the current- limit threshold is exceeded, the fault integration counter increments by one count. thus, if the current-limit condi- tion persists, the counter reaches its shutdown threshold in 32,768 counts and shuts down the external mosfets. when the max15034 shuts down due to a fault, the counter begins to count down (since the current-limit con- dition has ended), once every 16 clock cycles. thus, the device counts down for 524,288 clock cycles. at this point, switching resumes. this produces an effective duty cycle of 6.25% power-up and 93.75% power-down under fault conditions. with a switching frequency set to 250khz, power-up and power-down times are approxi- mately 131ms and 2.09s, respectively. control loop the max15034 uses an average current-mode control topology to regulate the output voltage. the control loop consists of an inner current loop and an outer volt- age loop. the inner current loop controls the output current, while the outer voltage loop controls the output voltage. the inner current loop absorbs the inductor pole, reducing the order of the outer voltage loop to that of a single-pole system. figure 2 is the block dia- gram of out1s control loop. the current loop consists of a current-sense resistor, r sense , a current-sense amplifier (ca1), a current- error amplifier (cea1), an oscillator providing the carri- er ramp, and a pwm comparator (cpwm1). the precision current-sense amplifier (ca1) amplifies the sense voltage across r sense by a factor of 36. the inverting input to cea1 senses the output of ca1. the output of cea1 is the difference between the voltage- error amplifier output (eaout1) and the gained-up volt- age from ca1. the rc compensation network connected to clp1 provides external frequency com- pensation for the respective cea1 (see the compensation section). the start of every clock cycle enables the high-side driver and initiates a pwm on- cycle. comparator cpwm1 compares the output volt- age from cea1 against a 0 to 2v ramp from the oscillator. the pwm on-cycle terminates when the ramp voltage exceeds the error voltage from the current-error amplifier (cea1). drive v in v out1 c out v ref = 0.61v r f c cff c cf i l r cf csn1 csp1 clp1 2v p-p r sense load r1 r2 ca 1 cea1 cpwm1 vea1 figure 2. current and voltage loops
max15034 configurable, single-/dual-output, synchronous buck controller for high-current applications 14 ______________________________________________________________________________________ the outer voltage control loop consists of the voltage- error amplifier (vea1). the noninverting input (ean1) is externally connected to the midpoint of a resistive volt- age-divider from out1 to ean1 to agnd. the voltage loop gain is set by using an external resistor from the output of this amplifier (eaout1) to its inverting input (ean1). the noninverting input of (vea1) is connected to the 0.61v internal reference. current-error amplifier the max15034 features two dedicated transconduc- tance current-error amplifiers cea1 and cea2 with a typical g m of 550s and 320a output sink and source capability. the current-error amplifier outputs (clp1 and clp2) serve as the inverting input to the pwm compara- tors. clp1 and clp2 are externally accessible to pro- vide frequency compensation for the inner current loops (see c cff , c cf , and r cf in figure 2). compensate the current-error amplifier so that the inductor current down slope, which becomes the up slope at the inverting input of the pwm comparator, is less than the slope of the internally generated voltage ramp (see the compensation section). pwm comparator and r-s flip-flop the pwm comparator (cpwm1 or cpwm2) sets the duty cycle for each cycle by comparing the current- error amplifier output to a 2v p-p ramp. at the start of each clock cycle an r-s flip-flop resets and the high- side drivers (dh1 and dh2) turn on. the comparator sets the flip-flop as soon as the ramp voltage exceeds the current-error amplifier output voltage, thus terminat- ing the on-cycle. voltage-error amplifier the voltage-error amplifier (vea_) sets the gain of the voltage control loop. its output clamps to 1.14v and -0.234v relative to v cm = 0.61v. set the max15034 out- put voltage by connecting a voltage-divider from the output to ean_ to gnd (see figure 4). at no load, the output of the voltage error amplifier is zero. use the equation below to calculate the no load voltage: the voltage at full load is given by: where ? v out is the voltage-positioning window described in the adaptive voltage positioning section. adaptive voltage positioning powering new-generation ics requires new techniques to reduce cost, size, and power dissipation. voltage positioning (figure 5) reduces the total number of out- put capacitors to meet a given transient response requirement. setting the no-load output voltage slightly higher than the output voltage during nominally loaded conditions allows a larger downward voltage excursion when the output current suddenly increases. regulating at a lower output voltage under a heavy load allows a larger upward-voltage excursion when the output current suddenly decreases. a larger allowed voltage-step excursion reduces the required number of output capacitors and/or allows the use of higher esr capacitors. the max15034 internal 0.6125v reference provides a tolerance of 1.25%. using 0.1% resistors for r1 and r2 allows a 4% variation from the nominal output volt- age. this available voltage range allows the reduction of the total number of output capacitors to meet a given transient response requirement resulting in a voltage- positioning window as shown in figure 5. from the allowable voltage-positioning window calcu- late the value of r f from the equation below. where ? v out is the allowable voltage-positioning win- dow, r sense is the sense resistor, 36 is the current- sense amplifier gain, and r 1 is as shown in figure 4. r ir r v f out sense out = 36 1 ? v r r v out fl out () . =+ ? ? ? ? ? ? ? 0 6125 1 1 2 ? v r r out nl () . =+ ? ? ? ? ? ? 0 6125 1 1 2
max15034 mosfet gate drivers (dh_, dl_) the high-side drivers (dh1 and dh2) and low-side dri- vers (dl1 and dl2) drive the gates of external n-channel mosfets. the high-peak sink and source current capa- bility of these drivers provides ample drive for the fast rise and fall times of the switching mosfets. faster rise and fall times result in reduced switching losses. for low- output, voltage-regulating applications where the duty cycle is less than 50%, choose high-side mosfets (q2 and q4, figure 6) with a moderate r ds(on) and a very low gate charge. choose low-side mosfets (q1 and q3, figure 6) with very low r ds(on) and moderate gate charge. the driver block also includes a logic circuit that provides an adaptive nonoverlap time (30ns typ) to pre- vent shoot-through currents during transition. figure 7 shows the dual-phase, single-output buck regulator. 2 x f sw (v/s) ramp clk csp_ csn_ gm in en_ 1.225v clp_ v dd bst_ dh_ lx_ dl_ pgnd a v = 36v/v pwm comparator s r q q g m = 500 s figure 3. current comparator and mosfet driver logic load c out v out v ref = 0.61v r f r 1 r 2 ean_ eaout_ figure 4. voltage error amplifier load (a) v cntr no load 1/2 load full load voltage-positioning window v cntr + ? v out /2 v cntr - ? v out /2 figure 5. defining the voltage-positioning window configurable, single-/dual-output, synchronous buck controller for high-current applications ______________________________________________________________________________________ 15
max15034 configurable, single-/dual-output, synchronous buck controller for high-current applications 16 ______________________________________________________________________________________ r t 24.9k ? r8 29.4k ? v reg r5 4.64k ? r4 1.74k ? c6 680 f 0.8v/10a r1 2m ? l1 0.5 h q1 irf7832 q2 irf7821 c8 0.1 f d1 (100ma, 30v) c2 1 f q4 irf7821 d2 (100ma, 30v) c3 0.1 f c4 4.7 f r3 1 ? c5 10 f v in 1.3v/10a c9 0.1 f q3 irf7832 l2 0.8 h r2 2m ? r14 1k ? c10 15nf c11 120pf r15 1k ? c12 15nf c13 120pf agnd avglimit v reg rt/clkin en2 pgnd en1 eaout1 ean1 csp1 csn1 dl1 lx1 dh1 bst1 v dd in reg bst2 dh2 lx2 dl2 pgnd csp2 csn2 ean2 eaout2 mode clp1 clp2 max15034 c7 680 f r9 60.4k ? r7 4.75k ? r6 5.11k ? external frequency sync 22 ? 22 ? r16 100k ? r17 100k ? c14 0.1 f c15 0.1 f r19 10k ? r18 19.6k ? figure 6. dual-output buck regulator
max15034 r t 24.9k ? r8 60.4k ? r5 4.75k ? r4 5.11k ? c6 680 f 1.3v/20a r1 2m ? l1 0.8 h q1 irf7832 q2 irf7821 c8 0.1 f d1 (100ma, 30v) c2 1 f q4 irf7821 d2 (100ma, 30v) c3 0.1 f c4 4.7 f r3 1 ? c5 10 f v in c9 0.1 f q3 irf7832 l2 0.8 h r2 2m ? r14 1k ? c10 15nf c11 120pf r15 1k ? c12 15nf c13 120pf agnd avglimit rt/clkin en2 en1 eaout1 ean1 csp1 csn1 dl1 lx1 dh1 bst1 v dd in reg bst2 dh2 lx2 dl2 pgnd csp2 csn2 ean2 eaout2 mode clp1 clp2 max15034 external frequency sync 22 ? 22 ? to reg v reg r16 100k ? r17 100k ? c14 0.1 f c15 0.1 f pgnd figure 7. dual-phase, single-output buck regulator configurable, single-/dual-output, synchronous buck controller for high-current applications ______________________________________________________________________________________ 17
max15034 configurable, single-/dual-output, synchronous buck controller for high-current applications 18 ______________________________________________________________________________________ design procedures inductor selection the switching frequency per phase, peak-to-peak ripple current in each phase, and allowable voltage ripple at the output, determine the inductance value. selecting higher switching frequencies reduces the inductance requirement, but at the cost of lower efficiency due to the charge/discharge cycle of the gate and drain capacitances in the switching mosfets. the situation worsens at higher input voltages, since capacitive switching losses are proportional to the square of the input voltage. lower switching frequencies on the other hand increase the peak-to-peak inductor ripple current ( ? i l ), and therefore, increase the mosfet conduction losses (see the power mosfet selection section for a detailed description of mosfet power loss). when using higher inductor ripple current, the ripple can- cellation in the multiphase topology, reduces the input and output capacitor rms ripple current. use the follow- ing equation to determine the minimum inductance value: choose ? i l to be equal to approximately 30% of the out- put current per channel. since ? i l affects the output-rip- ple voltage, the inductance value may need minor adjustment after choosing the output capacitors for full- rated efficiency. choose inductors from the standard high-current, surface-mount inductor series available from various manufacturers. particular applications may require custom-made inductors. use high-frequency core material for custom inductors. high ? i l causes large peak-to-peak flux excursion increasing the core losses at higher frequencies. the high-frequency operation cou- pled with high ? i l , reduces the required minimum induc- tance and even makes the use of planar inductors possible. the advantages of using planar magnetics include low-profile design, excellent current sharing between phases due to the tight control of parasitics, and low cost. for example, the minimum inductance at v in = 12v, v out = 0.8v, ? i l = 3a, and f sw = 500khz is 0.5h. the average current-mode control feature of the max15034 limits the maximum inductor current, which prevents the inductor from saturating. choose an inductor with a saturating current greater than the worst-case peak inductor current: where 24.75mv is the maximum average current-limit threshold for the current-sense amplifier and r sense is the sense resistor. power mosfet selection when choosing the mosfets, consider the total gate charge, r ds(on) , power dissipation, the maximum drain-to-source voltage, and package thermal imped- ance. the product of the mosfet gate charge and on- resistance is a figure of merit, with a lower number signifying better performance. choose mosfets opti- mized for high-frequency switching applications. the average gate-drive current from the max15034s output is proportional to the total capacitance it drives at dh1, dh2, dl1, and dl2. the power dissipated in the max15034 is proportional to the input voltage and the average drive current. see the supply voltage connections (v in /v reg ) and the low-side mosfet drives supply (v dd ) sections to determine the maxi- mum total gate charge allowed from all driver outputs together. the losses may be broken into four categories: conduc- tion loss, gate drive loss, switching loss, and output loss. the following simplified power loss equation is true for both mosfets in the synchronous buck-converter: for the low-side mosfet, the p switch term becomes virtually zero because the body diode of the mosfet is conducting before the mosfet is turned on. tables 1 and 2 describe the different losses and shows an approximation of the losses during that period. input capacitance the discontinuous input-current waveform of the buck converter causes large ripple currents in the input capacitor. the switching frequency, peak inductor cur- rent, and the allowable peak-to-peak voltage ripple reflected back to the source, dictate the capacitance requirement. increasing the number of phases increas- es the effective switching frequency and lowers the peak-to-average current ratio, yielding lower input capacitance requirement. it can be shown that the worst-case rms current occurs when only one con- troller section is operating. the controller section with the highest output power needs to be used in determin- ing the maximum input rms ripple current requirement. increasing the output current drawn from the other out- of-phase controller section results in reducing the input pp p pp loss conduction gatedrive switch outp =+ ++ u ut i r i l peak sense l _ . = + ? 24 75 10 2 3 ? l vv v vf i out in max out in sw l = ? () () ?
max15034 ripple current. a low-esr input capacitor that can han- dle the maximum input rms ripple current of one chan- nel must be used. the maximum rms capacitor ripple current is given by: where i max is the full load current of the regulator. v out is the output voltage of the same regulator and c in is c5 in figure 6. the esr of the input capacitors wastes power from the input and heats up the capacitor. reducing the esr is important to maintain a high overall efficiency and in reducing the heating of the capacitors. output capacitors the worst-case peak-to-peak inductor ripple current, the allowable peak-to-peak output ripple voltage, and the maximum deviation of the output voltage during step loads determine the capacitance and the esr requirements for the output capacitors. the output rip- ple can be approximated as the inductor current ripple multiplied by the output capacitors esr (r esr_out ). the peak-to-peak inductor current ripple is given by: during a load step, the allowable deviation of the output voltage during the fast transient load dictates the output capacitance and esr. the output capacitors supply the load step until the controller responds with a greater duty cycle. the response time (t response ) depends on the closed-loop bandwidth of the regulator. the resistive drop across the capacitors esr and capacitor discharge causes a voltage drop during a load step. use a combi- nation of sp polymer and ceramic capacitors for better transient load and ripple/noise performance. ? i vd lf l out sw = ? () 1 ii vvv v cin rms max out in out in () () ? loss description segment loss conduction loss losses associated with mosfet on-time and on-resistance. i rms is a function of load current and duty cycle. gate drive loss losses associated with charging and discharging the gate capacitance of the mosfet every cycle. use the mosfets (q g ) specification. switching loss losses during the drain voltage and drain current transitions for every switching cycle. losses occur only during the q gs2 and q gd time period and not during the initial q gs1 period. the initial q gs1 period is the rise in the gate voltage from zero to v th. r dh_ is the high- side mosfet drivers on-resistance and r gate is the internal gate resistance of the high-side mosfet (q gd and q gs2 are found in the mosfet data sheet). output loss losses associated with q oss of the mosfet occur every cycle when the high-side mosfet turns on. the losses are caused by both mosfets, but are dissipated in the high-side mosfet. table 1. high-side mosfet losses pir where i v v conduction rms ds on rms out in = ? 2 () i i load pvqqf gatedrive dd g gd sw = () ? pvi switch in loa = d dsw gs gd gate f qq i + () 2 gate dd dh where i v r = ( _ 2 + + r gate ) = + p qq vf output oss hs oss ls in sw () () 2 configurable, single-/dual-output, synchronous buck controller for high-current applications ______________________________________________________________________________________ 19
max15034 configurable, single-/dual-output, synchronous buck controller for high-current applications 20 ______________________________________________________________________________________ keep the maximum output-voltage deviation less than or equal to the adaptive voltage-positioning window ( ? v out ). during a load step, assume a 50% contribu- tion each from the output capacitance discharge and the voltage drop across the esr ( ? v out = ? v esr_ out + ? v q_ out ). use the following equations to calculate the required esr and capacitance value: where i load_step is the step in load current and t response is the response time of the controller. controller response time depends on the control-loop bandwidth. c out is c6 and c7 in figure 6. current limit the max15034 incorporates two forward current-limit protection mechanisms, average current limit and hic- cup fault current limit, which accurately limit the output current per phase. the average current-mode control technique of the max15034 accurately limits the maxi- mum average output current per phase. the max15034 senses the voltage across either a sense resistor or can implement lossless inductor sense, sensing the voltage across the parasitic resistance of the inductor (dcr). use either mechanism to limit the maximum inductor current. the minimum average voltage, at which the voltage across the current-sense resistor is clamped, is either internally set to 20.4mv or is controlled by the voltage at avglimit. the avglimit ground threshold of 550mv (typ) is the threshold above which the control of the average current-limit voltage is transferred from the internal 20.4mv (min) reference to the externally set v avglimit . for using the internal average current-limit value, short avglimit to agnd. the minimum (inter- nally set) average current limit is set at: for example, the current-sense resistor: for a maximum output current limit of 10a. a standard value is 2m ? . also, adjust the value of the current- sense resistor to compensate for parasitics associated with the pcb. select a noninductive resistor with an appropriate wattage rating. the implementation is shown in figure 8. when sensing directly across the inductor, connect an rc circuit directly across the shunt or inductor (see figure 9). r mv a m sense == 20 4 10 204 . . ? i mv r limit min sense () . = 20 4 r v i c it v esr out esr out load step out load step response q out _ _ _ _ _ = = ? ? loss description segment losses conduction loss losses associated with mosfet on-time, i rms is a function of load current and duty cycle. gate drive loss losses associated with charging and discharging the gate of the mosfet every cycle. there is no q gd charging involved in this mosfet due to the zero-voltage turn-on. the charge involved is (q g - q gd ). table 2. low-side mosfet losses pir where i vv v i conduction rms ds on rms in out in load = ? 2 () pvqqf gatedrive dd g gd sw = () ? note: the gate drive losses are distributed between the drivers and the mosfets in the ratio of the gate drivers resistance and the mosfets internal gate resistance.
max15034 set the rc time constant to be 1.1 to 1.2 times the inductor time constant (l/dcr). select c1 to be in the 0.1f to 0.47f range, and then calculate r1 from: in some applications, it may be useful to add a resistor (r2 in figure 9) in series with the csn_ connection to minimize input offset error. set r2 equal to r1. it may also prove useful to add capacitor c3 (figure 9) in parallel with r2 to aid in short-circuit recovery. set c3 equal to c1. finally, it may be helpful to add a 100pf (c2) capacitor immediately across the csp_ and csn_ inputs to minimize high-frequency noise pick-up at the ic in some applications. for current-sense resistors that have a noticeable inductance component, use lossless inductor sense implementation (and design procedure). see figure 10. table 3 highlights the tradeoffs of each current-sense method. rk lh dcr m c f 1 12 1 [] .[] [] [] ? ? = configurable, single-/dual-output, synchronous buck controller for high-current applications ______________________________________________________________________________________ 21 l out r sense v out lx_ csp_ max15034 csn_ figure 8. noninductive resistive sense l inductor dcr v out lx_ csp_ max15034 csn_ c2* r1 c1 c3* *optional. r2* figure 9. lossless inductor sense table 3. current-sense configurations method current-sense accuracy inductor-saturation protection current-sense power loss (efficiency) output current-sense resistor high allowed (highest accuracy) r sense x i out 2 equivalent inductor dc resistance low allowed no additional loss
max15034 configurable, single-/dual-output, synchronous buck controller for high-current applications 22 ______________________________________________________________________________________ the max15034 provides precision average current-limit programmability while using standard sense resistors or shunts. use the equation below to determine the appropriate v avglimit external reference voltage at avglimit: for example, assuming the desired average current limit is 18a, and r sense = 2m ? . where r sense is determined from maximum load cur- rent, wattage rating, and circuit parasitics (see above) and i load(max) from circuit requirements. v avglimit is the average current-limit reference voltage selected for a desired i load(max) and is set by a resistive voltage- divider from reg to agnd. see the programming the average current limit section. the second current-protection circuit is the hiccup fault protection as explained in the hiccup fault protection section. the average current during a short at the out- put is given by: programming the average current limit the max15034 average current-limit reference voltage is set by connecting a resistor-divider network from reg to agnd, the center node is connected to avglimit. the resistive dividers upper resistor, r1, is connected between reg and the avglimit. the resis- tive dividers lower resistor, r2, is connected between the avglimit and agnd. the resistor-divider values are determined by first, choosing r2. to minimize reference noise select r2 such that (r1 + r2) < 100k ? ; a typical value is 10k ? . next, determine r1 from: from the example above, assuming v avglimit = 1.91v: a standard value for r1 is 16.2k ? . connect avglimit to agnd for default current limit 20 4 . . mv r sense ? ? ? ? ? ? rk v v k 110 5 191 11618 = ? ? ? ? ? ? ? = ?? . . rr v v k v v reg avglimit avglimt 12 1 10 5 = ? ? ? ? ? ? ? = ? ( () [] max v ? ? ? ? ? ? ? 1 ii avg short load max () () . = 0 0625 vmamv mv v avglimit = () + == 2 36 18 612 5 1910 1 91 ? . . vrmia avglimit sense load max = () + 56 [ ] [ ] () ? 6 612 5 .m v esl sense resistor (inductive) r sense v out lx_ csp_ max15034 csn_ c2 r1 c1 c3 r2 l out figure 10. inductive sense resistor
max15034 reverse current limit the max15034 limits the reverse current when the out- put capacitor voltage is higher than the preset output voltage. calculate the maximum reverse current limit based on v clmp_lo and the current-sense resistor r sense . output-voltage setting the output voltage is set by the combination of resistors r1, r2, and r f as described in the voltage-error amplifier section. first select a value for resistor r2. then calculate the value of r1 from the following equation: where v out(nl) is the voltage at no load. then find the value of r f from the following equation: where ? v out is the allowable drop in voltage from no load to full load. r f is r8 and r9, r1 is r4 and r6, r2 is r5 and r7 in figure 6. compensation the max15034 uses an average current-mode control scheme to regulate the output voltage (see figure 2). the main control loop consists of an inner current loop and an outer voltage loop. the voltage error amplifier (vea1 and vea2) provides the controlling voltage for the current loop in each phase. the output inductor is hidden inside the inner current loop. this simplifies the design of the outer voltage control loop and also improves the power-supply dynamics. the objective of the inner current loop is to control the average inductor current. the gain-bandwidth characteristic of the cur- rent loop can be tailored for optimum performance by the compensation network at the output of the current- error amplifier (cea1 or cea2). compared with peak current-mode control, the current-loop gain crossover frequency, f c , can be made approximately the same, but the gain at low frequencies is much higher. this results in the following advantages over peak current- mode control. 1) the average current tracks the programmed cur- rent with a high degree of accuracy. 2) slope compensation is not required, but there is a limit to the loop gain at the switching frequency to achieve stability. 3) noise immunity is excellent. 4) the average current-mode method can be used to sense and control the current in any circuit branch. for stability of the current loop, the amplified inductor- current downslope at the negative input of the pwm comparator (cpwm1 and cpwm2) must not exceed the ramp slope at the comparators positive input. this puts an upper limit on the current-error amplifier gain at the switching frequency. the inductor current downs- lope is given by v out /l where l is the value of the inductor (l1 and l2 in figure 6) and v out is the output voltage. the amplified inductor current downslope at the negative input of the pwm comparator is given by: where r sense is the current-sense resistor (r1 and r2 in figure 6) and g m x r cf is the gain of the current-error amplifier (cea_) at the switching frequency. the slope of the ramp at the positive input of the pwm comparator is 2v x f sw . use the following equation to calculate the maximum value of r cf (r14 or r15 in figure 6). the highest crossover frequency f cmax is given by: or alternatively: equation (1) can now be rewritten as: r fl vr g cf c in s m = 9 2 () f fv v sw cmax out in = 2 f fv v cmax sw in out = 2 r fl vr g cf sw out sense m 2 36 1 () ? ? v t v l rgr l out sense m c f = 36 r ir r v f out sense out = 36 1 ? r v r out nl 1 0 6125 0 6125 2 (.) . () = ? i r reverse sense = ? 155 10 3 . configurable, single-/dual-output, synchronous buck controller for high-current applications ______________________________________________________________________________________ 23
max15034 in practical applications, pick the crossover frequency (f c ) in the range of: first calculate r cf in equation 2 above. calculate c cf so that: where c cf is c10 and c12 in figure 6. calculate c cff so that: where c cff is c11 and c13 in figure 6. applications information independent turn-on and turn-off the max15034 can be used to regulate two outputs from one controller. each of the two outputs can be turned on and off independently of one another by con- trolling the enable input of each phase (en1 and en2). a logic-low on each enable pin shuts down the mosfet drivers for that phase. when the voltage on the enable pin exceeds 1.2v, the drivers are turned on and the output can come up to regulation. this method of turning on the outputs allows the max15034 to be used for power sequencing. pcb layout guidelines careful pcb layout is critical to achieve low losses, low output noise, and clean and stable operation. this is especially true for dual-phase converters where one channel can affect the other. use the following guide- lines for pcb layout: 1) place the v dd , reg, and the bst1 and bst2 bypass capacitors close to the max15034. 2) minimize all high-current switching loops. 3) keep the power traces and load connections short. this practice is essential for high efficiency. use thick copper pcbs (2oz or higher) to enhance effi- ciency and minimize trace inductance and resis- tance. 4) run the current-sense lines csp_ and csn_ very close to each other to minimize loop areas. do not cross these critical signal lines through power cir- cuitry. sense the current right at the pads of the current-sense resistors. 5) place the bank of output capacitors close to the load. 6) isolate the power components on the top side from the analog components on the bottom side with a ground plane in between. 7) provide enough copper area around the switching mosfets, inductors, and sense resistors to aid in thermal dissipation and reducing resistance. 8) distribute the power components evenly across the top side for proper heat dissipation. 9) keep agnd and pgnd isolated and connect them at one single point close to the ic. do not connect them together anywhere else. 10) place all input bypass capacitors for each input as close to each other as is practical. c fr cff ccf = 1 210 c fr cf ccf = 10 2 f f f sw c sw 10 2 << configurable, single-/dual-output, synchronous buck controller for high-current applications 24 ______________________________________________________________________________________
max15034 configurable, single-/dual-output, synchronous buck controller for high-current applications ______________________________________________________________________________________ 25 28 27 26 25 24 23 22 21 20 19 18 17 16 15 1 2 3 4 5 6 7 8 9 10 11 12 13 14 en2 bst2 dh2 lx2 dl2 pgnd en1 in reg v dd dl1 lx1 dh1 bst1 csn1 csp1 eaout1 ean1 clp1 mode agnd rt/clkin avglimit clp2 ean2 eaout2 csp2 csn2 tssop top view max15034 *exposed pad *connect exposed pad to ground plane. max15034a does not have an exposed pad. + pin configuration chip information process: bicmos package information for the latest package outline information and land patterns (footprints), go to www.maxim-ic.com/packages . note that a +, #, or - in the package code indicates rohs status only. package drawings may show a different suffix character, but the drawing pertains to the package regardless of rohs status. package type package code outline no. land pattern no. 28 tssop u28+2 21-0066 90-0171 28 tssop-ep u28e+4 21-0108 90-0146
max15034 configurable, single-/dual-output, synchronous buck controller for high-current applications maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a maxim product. no circu it patent licenses are implied. maxim reserves the right to change the circuitry and specifications without notice at any time. the parametric values (min and max limits) shown in the electrical characteristics table are guaranteed. other parametric values quoted in this data sheet are provided for guidanc e. 26 ____________________maxim integrated products, 120 san gabriel drive, sunnyvale, ca 94086 408-737-7600 ? 2011 maxim integrated products maxim is a registered trademark of maxim integrated products, inc. max15034 revision history revision number revision date description pages changed 0 7/08 initial release 1 10/11 updated ordering information .1

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